Verilog HDL para hardware de IA

Verilog HDL para hardware de IA

Anil Kumar Sahu / Hemlata Sinha

72,02 €
IVA incluido
Disponible
Editorial:
KS OmniScriptum Publishing
Año de edición:
2026
ISBN:
9786630073959
72,02 €
IVA incluido
Disponible

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O rápido crescimento da Inteligência Artificial (IA), das Redes Neurais Artificiais (RNA) e das Redes Neurais Profundas (RNP) criou uma forte procura por aceleradores de hardware de alto desempenho, baixo consumo de energia e eficientes. As aplicações modernas de redes neurais envolvem um grande número de operações computacionais, nas quais a unidade de multiplicação-acumulação (MAC) desempenha um papel fundamental na execução dos processos de multiplicação e acumulação. Uma vez que as operações MAC dominam os cálculos neurais, a otimização da arquitetura MAC melhora diretamente o desempenho global dos aceleradores de IA. Este livro apresenta o projeto e a implementação em FPGA de uma arquitetura MAC em pipeline, de alta velocidade e eficiente em termos de área, para a aceleração de redes neurais utilizando Verilog HDL. A arquitetura proposta integra um multiplicador Vedic para a geração rápida e paralela de produtos parciais e um somador de seleção de transporte de raiz quadrada (SQRT-CSLA) baseado num conversor binário para excesso de 1 (BEC) para uma acumulação eficiente. Este trabalho destina-se a estudantes, investigadores, projetistas de FPGA e profissionais de VLSI interessados no desenvolvimento de soluções de hardware eficientes para aplicações de IA e aprendizagem profunda da próxima geração.

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