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PVT-variationsbewusster, stromsparender Vedic-Multiplikator für DSPs auf FPGAs

PVT-variationsbewusster, stromsparender Vedic-Multiplikator für DSPs auf FPGAs

Bishwajeet Pandey / Kavita Goswami

102,76 €
IVA incluido
Disponible
Editorial:
KS OmniScriptum Publishing
Año de edición:
2026
Materia
Tecnología: cuestiones generales
ISBN:
9786209926051
102,76 €
IVA incluido
Disponible

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Sobre IBD

Da die Kommunikations- und Signalverarbeitungsbranche rasant wächst, steigt die Nachfrage nach Multiplikatoren kontinuierlich und in hohem Tempo. Für Forscher ist die Entwicklung von schnellen und energieeffizienten Multiplikatoren ein zentrales Anliegen. Eine Reduzierung des Stromverbrauchs und der Verzögerung einer Multiplikatorschaltung dürfte eine Revolution im Bereich der Elektronik und Kommunikation bewirken. Die Leistung eines Systems wird im Allgemeinen durch die Leistung des Multiplikators bestimmt, da dieser in der Regel das langsamste Element im System ist. Daher ist die Optimierung der Geschwindigkeit und des Stromverbrauchs des Multiplikators ein zentrales Designproblem. Es besteht Bedarf an der Entwicklung von schnellen und stromsparenden Multiplikatoren für Algorithmen der digitalen Signalverarbeitung. Aus früheren Forschungen wurde geschlossen, dass vedische Multiplikatoren effizienter sind als herkömmliche Multiplikatoren. In dieser Arbeit wird ein stromsparender vedischer Multiplikator vorgeschlagen.

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