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Conception d’un multiplicateur védique basse consommation tenant compte des variations PVT pour les DSP sur FPGA

Conception d’un multiplicateur védique basse consommation tenant compte des variations PVT pour les DSP sur FPGA

Bishwajeet Pandey / Kavita Goswami

101,46 €
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Editorial:
KS OmniScriptum Publishing
Año de edición:
2026
Materia
Tecnología: cuestiones generales
ISBN:
9786209931178
101,46 €
IVA incluido
Disponible

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Sobre IBD

À mesure que les secteurs des communications et du traitement du signal se développent, la demande en multiplicateurs ne cesse d’augmenter à un rythme effréné. Pour les chercheurs, le développement de multiplicateurs à haute vitesse et à faible consommation d’énergie constitue un enjeu majeur. La réduction de la consommation d’énergie et du temps de propagation d’un circuit multiplicateur devrait révolutionner le domaine de l’électronique et des communications. Les performances d’un système sont généralement déterminées par celles du multiplicateur, car ce dernier est généralement l’élément le plus lent du système. Par conséquent, l’optimisation de la vitesse et de la consommation d’énergie du multiplicateur constitue un enjeu majeur de conception. Il est nécessaire de développer des multiplicateurs à haute vitesse et à faible consommation d’énergie pour les algorithmes de traitement des signaux numériques. Des recherches antérieures ont conclu que les multiplicateurs védiques sont plus efficaces que les multiplicateurs conventionnels. Dans ce travail, un multiplicateur védique à faible consommation d’énergie a été proposé.

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