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Formal Semantics and Proof Techniques for Optimizing VHDL Models

Formal Semantics and Proof Techniques for Optimizing VHDL Models

Kothanda Umamageswaran / Philip A. Wilsey / Sheetanshu L. Pandey

134,43 €
IVA incluido
Disponible
Editorial:
Springer Nature B.V.
Año de edición:
2012
Materia
Matemáticas
ISBN:
9781461373315
134,43 €
IVA incluido
Disponible

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Sobre IBD

Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.

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Otros libros del autor

  • Formal Semantics and Proof Techniques for Optimizing VHDL Models
    Kothanda Umamageswaran / Philip A. Wilsey / Sheetanshu L. Pandey
    Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. ...