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Formal Semantics and Proof Techniques for Optimizing VHDL Models

Formal Semantics and Proof Techniques for Optimizing VHDL Models

Kothanda Umamageswaran / Philip A. Wilsey / Sheetanshu L. Pandey

133,08 €
IVA incluido
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Editorial:
Springer Nature B.V.
Año de edición:
1998
Materia
Matemáticas
ISBN:
9780792383758

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Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.

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  • Formal Semantics and Proof Techniques for Optimizing VHDL Models
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    Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. ...
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