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Bezpieczeństwo działania systemu wnioskowania rozmytego w FPGA

Bezpieczeństwo działania systemu wnioskowania rozmytego w FPGA

Mohammed Bsiss

126,22 €
IVA incluido
Disponible
Editorial:
KS OmniScriptum Publishing
Año de edición:
2025
Materia
Empresa y gestión
ISBN:
9786208005191
126,22 €
IVA incluido
Disponible

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Sobre IBD

Wiarygodność systemu związanego z bezpieczeństwem można przeprowadzić za pomocą analizy jakościowej i ilościowej w celu powiązania poziomu nienaruszalności bezpieczeństwa (SIL). Analizy te opierają się na międzynarodowych standardach, takich jak norma IEC 61508 i norma ISA. Istnieją różne metody tworzenia tego typu analiz: schemat blokowy niezawodności (RBD), analiza drzewa błędów (FTA) oraz modele Markowa. W niniejszej książce zaproponowano analizę bezpiecznego sterownika logiki rozmytej (SFLC) zaimplementowanego w układzie FPGA o architekturze 1 z 2 (1oo2) i zastosowano dwie metody oceny. Pokazujemy, jak na podstawie parametrów charakterystyki sprzętu, takich jak wskaźnik niebezpiecznych wykrytych i niewykrytych awarii, pokrycie diagnostyczne, interwał testu dowodowego i inne parametry obliczyć średnie prawdopodobieństwo niebezpiecznej awarii na żądanie, a w konsekwencji określić poziom nienaruszalności bezpieczeństwa (SIL) dla SFLC.

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