LNA-ESD Co-Design for Fully Integrated CMOS Wireless Receivers

Abstract. List of Symbols and Abbreviations. 1 Introduction. 1.1 The Growth of the Wireless Communication Market. 1.2 Evolution to CMOS RF. 1.3 CMOS, RF and ESD. 1.4 Outline of this Book. 2 Low-Noise Amplifiers in CMOS Wireless Receivers. 2.1 Introduction. 2.2 Some Important RF Concepts. 2.2.1 Quality Factor of Reactive Elements and Series-Parallel Transformation. 2.2.2 SNR and Noise Figure. 2.2.3 Impedance Matching, Power Matching, Noise Matching. 2.2.4 Transducer Power Gain, Operating Power Gain and Available Power Gain. 2.2.5 Intermodulation Distortion. 2.3 The Deep Sub-Micron MOS Transistor at Radio Frequencies. 2.3.1 MOS Model for Hand Calculations. 2.3.2 Linearity of the short-channel MOS transistor. 2.3.3 Non-Quasi Static Model. 2.3.4 Extended MOS Model for Simulation. 2.4 The Origin of Noise. 2.4.1 Resistor Thermal Noise. 2.4.2 Thermal Noise in MOS transistors. 2.4.2.1 Classical MOS Channel Noise. 2.4.2.2 Induced Gate Noise. 2.4.3 1/f Noise. 2.4.4 Shot Noise. 2.5 The LNA in the Receiver Chain. 2.5.1 Cascading Non-Ideal Building Blocks. 2.5.1.1 Noise in a Cascade. 2.5.1.2 IIV3 of a Cascade. 2.5.2 Wireless Receiver Architectures. 2.5.3 LNA Requirements. 2.5.3.1 Matching. 2.5.3.2 Noise Figure. 2.5.3.3 Voltage Gain or Power Gain. 2.5.3.4 Intermodulation Distortion. 2.5.3.5 Reverse Isolation. 2.5.3.6 Stability. 2.5.3.7 Single-ended vs. Differential. 2.6 Topologies for Low-Noise Amplifiers. 2.6.1 The Inductively Degenerated Common Source LNA. 2.6.1.1 From Basic Common-Source Amplifier to Inductively Degenerated Common-Source LNA. 2.6.1.2 Power Gain. 2.6.1.3 Noise Figure. 2.6.1.4 Linearity. 2.6.2 The Common-Gate LNA. 2.6.2.1 Input Matching. 2.6.2.2 Power Gain. 2.6.2.3 Noise Figure. 2.6.2.4 Linearity. 2.6.3 Shunt-Feedback Amplifier. 2.6.4 Image Reject LNA’s. 2.6.5 Highly Linear Feedforward LNA. 2.6.6 The Noise-Cancelling Wide-band LNA. 2.6.7 Current Reuse LNA with Interstage Resonance. 2.6.8 Transformer Feedback LNA. 2.7Conclusion. 3 ESD Protection in CMOS. 3.1 Introduction. 3.2 ESD Tests and Standards. 3.2.1 Human Body Model. 3.2.2 Machine Model. 3.2.3 Charged Device Model. 3.2.4 Transmission Line Pulsing. 3.3 ESD-Protection in CMOS. 3.3.1 ESD-Protection Devices. 3.3.1.1 Diode. 3.3.1.2 Grounded-Gate NMOS. 3.3.1.3 Gate-Coupled NMOS. 3.3.1.4 Silicon-Controlled Rectifier. 3.3.2 ESD-Protection Topologies. 3.3.2.1 I/O Pins. 3.3.2.2 Power Supply Clamping. 3.4 Conclusion. 4 Detailed Study of the Common-Source LNA with Inductive Degeneration. 4.1 Introduction. 4.2 The Non-Quasi Static Gate Resistance. 4.2.1 Influence of rg;NQS on Zin, GT and IIP3. 4.2.2 Influence of rg;NQS on the Noise Figure. 4.3 Parasitic Input Capacitance. 4.3.1 Impact of Cp. 4.3.1.1 Influence of Cp on Input Matching. 4.3.1.2 Influence of Cp on Power Gain, Noise Figure and IIP3. 4.3.2 Impact of Cp Non-Linearity. 4.3.3 Impact of the Finite Q of Cp. 4.4 Miller Capacitance. 4.5 Optimization of the Cascode Transistor. 4.6 Output Capacitance Non-Linearity. 4.7 Impact of a Non-Zero S11 . 4.8 Output Considerations. 4.8.1 Load Impedance Constraints. 4.8.2 Output Matching. 4.9 LNA Bandwidth. 4.10 Layout Aspects. 4.10.1 RF Bonding Pads. 4.10.2 On-Chip Inductors. 4.10.2.1 Modelling. 4.10.2.2 Patterned Ground Shields. 4.10.3 The Amplifying Transistor. 4.10.4 The Cascode Transistor. 4.11 The Common-Gate LNA Revisited. 4.12 Conclusion. 5 RF-ESD Co-Design for CMOS LNA’s. 5.1 Introduction. 5.2 ESD-protection within an L-Type Matching Network. 5.2.1 Introduction. 5.2.2 General Performance. 5.2.3 Design and Layout of the ESD Protection Diodes. 5.2.4 Non-Linearity of Input ESD Protection Diodes. 5.2.5 Conclusion. 5.3 ESD-Protection within a _-Type Matching Network. 5.4 Inductive ESD-Protection. 5.5 Comparison. 5.6 Other ESD-Protection Strategies. 5.6.1 Distributed ESD-Protection. 5.6.2 ESD-Protection with T-Coils. 5.7 ESD-Protection for the Common-Gate LNA. 5.8 Conclusion. 6