Librería Samer Atenea
Librería Aciertas (Toledo)
Kálamo Books
Librería Perelló (Valencia)
Librería Elías (Asturias)
Donde los libros
Librería Kolima (Madrid)
Librería Proteo (Málaga)
Continuous scaling of transistors combined withincreased chip area results in the ratio of globalwire delay to gate delay increasing at a super-linearrate. Simple RC models have become inadequate forsimulation of VLSI circuits. In addition, parasiticinductance and capacitance of IC packages imposelimits on the circuit performance at RF frequencies.This book presents modeling of on-chip inductance forchips with ground grids that emulate those used inreal circuits. S-parameter characterization of testchips up to 10 GHz shows good agreement withsimulation and analytical calculations. On-chip 3-Dcapacitance modeling capabilities for arbitrarilyshaped objects are also presented. In addition, anapproach to fast 3-D modeling of the geometry forbonding wires in RF circuits and packages isdemonstrated. The geometry and an equivalent circuitare presented to model the frequency response ofbonding wires. Excellent agreement between modeledresults and measured data is achieved for frequenciesup to 10 GHz. The book should be useful to thesemiconductor professionals in academia and industry,who are interested in the on-chip and packageinterconnects researches.
